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European Semiconductor Innovation and Entrepreneurship 20 years past, 20 years ahead


Tuesday, September 12


Auditorium I

Europe has a long history of excellence in Semiconductor Innovation and Entrepreneurship. Over the past two decades, more than $11 billion have been invested in about 1,000 startups of which Dialog Semiconductor,  ARM Holdings, Imagination Technologies, Silex Microsystems,  Xmos, GreenWaves Technologies, Nanusens, Intellitronika are just a few among many others which have developed innovative technologies and solutions that are used in a wide range of industries and have achieved scale-up status and global prominance.


Today, possibly more than ever before, Europe can be at the forefront of disruption and innovation driven by mutually-feeding trends in AI and analog computation, IoT and edge computing, quantum and neuromorphic computing, optical processing, and solid-state photonic chips. Going forward, we will highlight the formidable challenges ahead, notably limited access to venture capital funding and value chain fragmentation, and discuss the 5 critical elements of the Entrepreneurship ecosystem that will strengthen competitiveness, drive growth and progress: Innovation,  Job Creation, Competition, Flexibility,  and Access to Talent.

José Epifânio da Franca

  • José Franca graduated in Electrical Engineering from Instituto Superior Técnico (1978), received the Ph.D. from Imperial College London (1985), and completed the executive program on Management of Research and Technology-based Innovation at the Sloan School of Management, Massachusetts Institute of Technology (1992). He is Professor at Instituto Superior Técnico where he founded the Integrated Circuits and Systems Group (1986), and was a member of the Management Board (1987-1991). His current areas of interest and expertise include entrepreneurship and innovation.

  • In 1997 José Franca co-founded and became CEO and Chairman of Chipidea Microelectronics which pioneered and became a worldwide leader in the Semiconductor Analog Mixed-Signal IP industry until his departure in 2008 upon the acquisition by MIPS Technologies. Currently with c. 700 engineers in Portugal, the former Chipidea operation is now the largest European engineering centre of Synopsys.

  • In 2012 José Franca was appointed by the Government of Portugal Chairman of the Board and CEO of Portugal Ventures, which he served until 2015 with the mandate to establish a modern, internationally recognized technology-based entrepreneurial ecosystem in Portugal laying out solid foundations for the attraction of international venture capital and steady worldwide inflows of talent and experience.

  • José Franca is Fellow of the IEEE (1997), recipient of the Golden Jubilee Medal (1999) and of the Industrial Pioneer Award (2010) of its Circuit and Systems Society. He is the winner of the 2008 University of Coimbra Prize, was bestowed the “Grande Oficial da Ordem do Mérito” by the President of Republic (2006), and awarded the “Doctor Honoris Causa” degree from University of Macau (2006).


Bringing circuits and communications back together, in a modular fashion


Tuesday, September 12


Auditorium I


In this talk, we present a vision of standards to help ensure both reliability and room for innovation. Current development of algorithms for communications and networking are often done separately from their circuit instantiations. The circuit design in turn takes multiple algorithms and embeds them in a monolithic architecture. We argue that standards can successfully concentrate on purely functional matters, relying on modular APIs, rather than being prescriptive about methods, which often embed inefficient legacy technologies. Within these modules, we argue that there are real benefits to creating or recreating tighter links between algorithmic development and circuit design. As a case study, we present recent developments in universal error-correcting decoding using guessing random additive noise decoding (GRAND). In that project, a close collaboration between the creation of decoders and of circuits leads to schemes that outperform the state of the art.

Muriel Médard

  • Muriel Médard is the NEC Professor of Software Science and Engineering in the Electrical Engineering and Computer Science (EECS) Department at MIT, where she leads the Network Coding and Reliable Communications Group in the Research Laboratory for Electronics at MIT and Chief Scientist for Steinwurf, which she has co-founded. She obtained three Bachelors degrees, as well as her M.S. and Sc.D, all from MIT. Muriel is a Member of the US National Academy of Engineering (elected 2020), a Member of the German National Academy of Sciences Leopoldina (elected 2022), a Fellow of the US National Academy of Inventors (elected 2018), American Academy of Arts and Sciences (elected 2021), and a Fellow of the Institute of Electrical and Electronics Engineers (elected 2008). She holds Honorary Doctorates from the Technical University of Munich (2020) and from The University of Aalborg (2022).

  • Muriel was awarded the 2022 IEEE Kobayashi Computers and Communications Award. She received the 2019 Best Paper award for IEEE Transactions on Network Science and Engineering, the 2018 ACM SIGCOMM Test of Time Paper Award, as well as nine conference paper awards. 

  • Muriel currently serves as the Editor-in-Chief of the IEEE Transactions on Information Theory. Muriel was elected president of the IEEE Information Theory Society in 2012, and serves on its board of governors, having previously served for eleven years.

  • Muriel received the inaugural MIT Postdoctoral Association Mentoring Award in 2022, the inaugural MIT EECS Graduate Student Association Mentor Award, voted by the students in 2013. She set up the Women in the Information Theory Society (WithITS) and Information Theory Society Mentoring Program, for which she was recognized with the 2017 Aaron Wyner Distinguished Service Award. She serves on the Nokia Bell Labs Technical Advisory Board. 

  • Muriel has over sixty US and international patents awarded, the vast majority of which have been licensed or acquired. For technology transfer, she has co-founded CodeOn, for which she consults, and Steinwurf, for which she is Chief Scientist.

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The Heart of Artificial Intelligence Advanced Power Semiconductors Enable Greener, Denser, and Smarter Datacenters

Wednesday, September 13


Auditorium I

As the demand for cloud computing, AI applications, machine learning, high performance computing, and supercomputers rapidly grows, datacenters are evolving to accommodate new, higher power requirements. Meanwhile, to optimize the Total Cost of Operation (TCO), datacenters demand for higher efficiency and higher density power solutions. Power has become one of the biggest challenges for a datacenter. With the advanced power semiconductor technologies, which includes device processes, packaging technologies, and system level design optimizations, analog/digital mixed signal circuit designs including power specific state machines, sensors, high precision ADC, and DSP ASIC.

The worldwide power community has been continuously pushing the boundaries to achieve the common goal: to enable a Greener, Denser, Smarter datacenter. Think of AI processor as a brain, power engine is simply the heart.


Eric Yang

  • Dr. Eric Yang received the B.S. and M.S. degree from Tsinghua University, in 1982 and 1984 respectively. In 1994, he received his PhD degree in electrical engineering from Virginia Polytechnic Institute and State University.

  • He then joined Harris Semiconductor as staff applications engineer working on high power semiconductor device and module development.  He moved to Silicon Valley in 1998 and joined Semtech Corp. as Senior Staff Engineer later Director of Applications, working on develop first generation of multi-phase CPU core voltage regulators. 

  • He joined Monolithic Power System (MPS) in 2006 as Senior Director of applications engineering and later became Vice President of Technical Marketing.  In past 17 years, Dr. Yang played an essential role to build MPS engineering teams, define new products, and develop of power management system IP’s. which cover computing/datacenter platforms, networking/communications, AC to DC power conversions, battery systems, automotive platforms, motor drives, and so on.

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Chip Architectures for Efficient Analog-to-Information Image Analysis using Out-the-Box Processing Concepts


Thursday, September 14


Auditorium I

Citius, altius, fortius, the Olympic motto, applies to the evolution of imagers fueled by CIS processes, and convergent packaging and heterogeneous integration technologies. Besides, embedding image analysis and, eventually, vision task capabilities everywhere defines one prevalent challenge of micro-system integration. However, conventional processing paradigms based on full image digitization and von Neumann processing architectures may not address this challenge adequately. Indeed, natural retinas, the most efficient imaging front-ends known to date, achieve outstanding energy efficiencies and data throughputs using different paradigms. Although retina behavior might not be exactly reproduced with micro-electronic technologies, the concepts and principles underlying its operation inspire “out-the-box” vision system chip architectures that handle images according to the Olympic motto. This talk overviews some most prominent concepts of a technology that is already starting to transition from academia to industrial usage.

Ángel Rodríguez-Vázquez

  • PhD in Physics-Electronics

  • Professor-University of Seville

  • Visiting Researcher/Professor  at Univ. of California-Berkeley, Texas A&M University and Pèter Pazmany University)

  • Co-Founder of the Institute of Microelectronics of Sevilla (Spanish Microelectronics Center)

  • Main promotor and first CEO of AnaFocus Ltd (today Teledyne-AnaFocus)

  • Consultor for ATMEL and ALCATEL (data converters) and E2V (smart imagers)

  • h-index=51; i10-index=226;~12,000 citations

  • 12 patents, extensive technology transfer activities and participation in 3STEs

  • Life Fellow of IEEE

  • Recipient of IEEE Van Valkenburgh award

  • Member of Academia Europaea

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Software Defined Radio for Next Generation Communication Networks


Wednesday, September 13


Auditorium I


Advanced CMOS process technology offers the prospect of migrating much of the RF signal chain to the digital domain with significant benefits in power, cost, performance and system simplification. As 5G / 6G radio spectrum and occupied radio bandwidths continue to expand, the RF performance and digital compute requirements increase exponentially. However, these requirements must be achieved without increasing power consumption, due to environmental and OPEX considerations as well as mechanical-thermal constraints. This Keynote will discuss possible paths forward to addressing these challenges in the areas of RF system architecture, compute optimisation, integration and process scaling.

Brendan Farley

  • Brendan Farley is Vice-President of Wireless Engineering at AMD andManaging Director of the Adaptive and Embedded Computing Group in Europe.He is based in Ireland where the company operates an advanced research,development, engineering and IT centre.

  • Brendan is responsible for a global, multi-disciplined team developing key technologies for wireless infrastructure which include silicon products such as the revolutionary RFSoC device family,  and IP solutions for beamforming, digital modulation and digital linearization of RF systems.

  • Brendan has more than 15 patents in RF microelectronics and digital signal processing, numerous peer reviewed publications and is a regular contributor at conferences and industry forums. He is a Senior Member of the IEEE and holds a Bachelor of Science Degree in Electronic Engineering from Trinity College Dublin and a Master of Science Degree in Technology Management from NUI Galway.

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High speed Wireline Transceivers

Past, Present and Future Wireline SerDes Transceivers: Evolution and Prospects for 224-Gb/s

Tuesday, September 12


Auditorium I

The progression towards ever faster transfer rates is necessarily facilitated by architectural enhancements within the SerDes transceiver. And further helped by the addition of forward error correction (FEC) to the link definition.   Electrical channels are simply not keeping pace.  As a result, SerDes complexity has increased dramatically. Here, transistor scaling has come to the rescue by enabling SerDes designers to shift from primarily analog to ADC-DSP solutions.  DSP solutions open the door to more complex equalization schemes and rich(er) mission-mode link diagnostics.  A state-of-the-art 224-Gb/s SerDes transceiver can be expected to include more than 40-tap FFE, 1-to-2 tap DFE, and MLSD. Moreover, final solutions will likely have extended diagnostic features that include statistical information from the FEC.  Even so, the 224-Gb/s challenge is significant.  In this talk, we review current progress in wireline transceivers and discuss prospects for the 212-Gb/s generation.

Dino Toffolon

  • Dino Toffolon joined Synopsys in 2002 and is currently Sr. Vice President of Engineering responsible for the Synopsys DesignWare IP Interface PHY product line.


  • Before joining Synopsys, Dino worked as a Circuit Design Engineer focused on high-speed video and baseband communication chips at Gennum Corporation and Cogency Semiconductor.


  • Dino has over 25 years of industry experience and has been issued over 20 patents in the field of high-speed circuits and communications. He holds a B.Eng. Mgt in Computer and Electrical Engineering as well as an M.B.A in Finance from McMaster University.

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Analog and Mixed-Signal CMOS Circuits: The emergence and leadership of a Lab, a reference Book and the future at the core of the A/D Interface in the IoE


Thursday, September 14


Auditorium I


The Analog/Digital Interface with Audio, Vision & Sensors, is essential for the Internet of Everything - IoE. The State Key Laboratory of Analog and Mixed-Signal VLSI from University of Macau (UM), with a history of 30+ years, emerged as such in 2011, being now world-renowned for its excellence in the design of innovative circuits for the analog/digital interface. In a recent book entitled “Analog and Mixed-Signal Circuits in Nanoscale CMOS”, we presented the most critical building blocks of such interface that need to exhibit high quality performance with low power consumption, high energy-efficiency and high speed. There is a huge pressure in the design area with a high demand for analog design engineers, opening a vast field of opportunities and challenges that imply a continuous knowledge update. UM is contributing to stimulate and well-equip the mind of future skillful analog design engineers in state-of-the-art designs adequate for most IoE applications.

Rui P. Martins

  • Rui Martins born in 1957, in Lisbon, Portugal, got the Ph.D. in Electrical Engineering and Computers from Instituto Superior Técnico (IST), Universidade de Lisboa (UL), Portugal, in 1992. He is a member of the Academic Staff of IST (Oct. 1980), on leave since October 1992. Since then he is with the Department of Electrical and Computer Engineering, Faculty of Science and Technology (FST), University of Macau (UM), Macao, China, where he is a Chair-Professor since Aug. 2013.

  • He authored 896 publications: 9 books and 12 book chapters; 50 Patents, USA (39), China (8) & Taiwan (3); 745 papers, in scientific journals (331) and in conference proceedings (414); as well as other 80 academic works.

  • He created in 2003 the Analog and Mixed-Signal VLSI Research Laboratory of UM, elevated in January 2011 to State Key Laboratory of China, being its Founding Director.

  • He is an IEEE Fellow (2008) and also the Director of the Institute of Microelectronics since January 2019, recognized in the 70th edition of ISSCC, in February 2023, as one of its “Top Contributors” with more than 50 papers. Since July 2010 he is an Academician in the Lisbon Academy of Sciences, Portugal.


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New Technologies and Innovative Architectures for the Augmented Reality, the Next Human-Machine Interfaces


Tuesday, September 12


Auditorium I


The human relationship with computers and information has evolved in a dramatic way in the last decades. Humanity encountered the first personal computer in the 50s, which eventually evolved on the Internet. Recent times have seen the revolution of the smart phone. Today, we’re immersed into a vast ocean of virtual information and connections whenever and wherever we want, through two-dimensional surfaces which accompany us everywhere we go. Clearly, the future of our digital gateways will be even more portable and personal in the future. At Facebook Reality Labs, we are developing the next generation computing platform, the AR/VR glasses which will combine virtual and real worlds, to serve human needs and to explore the limits of human experience. Silicon is only one piece of the many technologies that need to converge together to create a fully AR experience. We need to integrate Si together with displays, sensors, electrical and mechanical systems and not ultimately, AR algorithms. If the importance of performance-per watt is well known for mobile device, it will be even more critical for AR devices. In order to make this vision reality, we will need optimization at every level of the system, including novel revolutionary technologies and co-optimization of HW and SW.

Barbara De Salvo

  • Barbara De Salvo is Director of Research at Meta Reality Labs Research (USA), responsible for Silicon Strategy and Foundry Engineering. She influences topnotch semiconductor companies and academia to define the most optimized semiconductor technologies that will enable Meta’s next generation of human-machine-interface, the new Augmented Reality/Virtual Reality (AR/VR) platforms which combine virtual and real worlds to explore the limits of human experience. She leads a multi-disciplinary team, including technologists, Asic designers, Machine Learning (ML) algorithm-, Computer Vision- scientists, and system engineers to drive the introduction of novel semiconductor technologies and new computing paradigms (as Compute-In-Memory, On-Sensor-Compute) in next generation AR/VR product systems.

  • Before joining Meta in 2019, she was Chief Scientist and Deputy Director of CEA-LETI (France), driving the path-finding strategy. In CEA-LETI, she founded and led the advanced memory technology division (2008-2013), where she promoted the introduction of disruptive memory technologies, such as phase-change memories, resistive oxide-based and conductive-bridge memories and neuromorphic hardware solutions based on emerging technologies.

  • In 2013-2015, she was manager and visiting scholar in IBM-Albany-NY (USA) in the frame of the sub-10nm CMOS International Technology Alliance, where several of her research works have led to product technologies for novel logic ICs (as Silicon-On-Insulator, Finfet and stacked nanowire technology platforms).

  • She has authored more than 350 referred articles, ten book chapters, a monography on Silicon Non-Volatile Memories edited by Wiley and Sons. She served as General Chair of  IEEE IEDM 2022, as well as chair of the IEEE Corporation Award Committee (2021, 2022).

  • She is a Fellow of the IEEE, and an active member of the IEEE Women in Engineering network.

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Oxide thin-film transistors: are we reinventing electronics? Or dressing an old story with today’s clothes?

Wednesday, September 13


Auditorium I

With the current constrains on assuring supply of microelectronic chips and on technological/ physical limitations to further miniaturize existing Si-based transistors, the world is looking for alternative approaches to revolutionize electronics. Thin-film transistors (TFTs) have been fueling flat panel display industry for the last 3 decades, and with oxide semiconductors enabling a combination of good electrical performance, low-temperature/large area fabrication and even optical transparency, academics and industry are pushing the boundaries for these devices and taking them to applications beyond displays. Indeed, oxide TFTs are now finding their application space in multiple domains: from low-transistor count flexible circuits that can be seamlessly embedded into everyday objects, to high-density circuits with sub-10 nm gate lengths, where arguments such as compatibility with non-planar device structures (e.g., gate-all-around) and extremely low off-currents turn the technology very appealing for a new wave of electronic applications, where sustainability and high-performance can mutually exist.

Pedro Barquinha

  • Pedro Barquinha received his PhD in Nanotechnologies and Nanosciences from NOVA University Lisbon in 2010. He is currently Associate Professor at the Materials Science Department of FCT-NOVA and group leader of Materials for Electronics, Optoelectronics and Nanotechnology at CENIMAT|I3N.

  • Low-temperature oxide electronics has been his core research since 2004, including thin film deposition, nanostructure synthesis and their integration in flexible devices such as transistors, circuits and nanogenerators.

  • This has been achieved through >40 research projects with academia and industry, including an ERC Starting Grant (TREND) and an ERC Proof of Concept Grant (FLETRAD). He co-authored more than 170 peer-reviewed papers (h-index=54, as March 2023), 3 books and 7 book chapters and is an editor at IEEE Electron Device Letters and IEEE Journal of Flexible Electronics.

  • Since 2022 he is a member of the Portuguese Council for Science, Technology and Innovation and a member of the International Iberian Nanotechnology Laboratory (INL) council.

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Silicon Technology Innovation Opportunities for Applications at 0.1 to 1 THz Beyond that for Transistors

Thursday, September 14


Auditorium I

The wide frequency bands that can become available and smaller wavelengths at 0.1 to 1 THz hold the promise for enabling tera-bps communication, and higher resolution radar imaging in visually impaired conditions at a given form factor. This frequency range can also be utilized to detect a wide variety of gases and to measure concentrations.  This presentation reviews the state of art for electronics performance in this frequency range that has rapidly advanced over the past decade. Two application examples, 420-GHz imaging and 300-GHz high bandwidth wireless communication are then examined. From this, opportunities for improvement, such as that for noise performance, output power and power efficiency, as well as additional required capabilities such as low-cost testing, packaging and electronically steerable reflectarray are identified, and the technology innovation beyond that for transistors, which can mitigate or overcome the limitations and support the additional necessary capabilities are discussed.

Kenneth O

  • Kenneth O received his Ph.D. degree in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology in 1989.

  • From 1989 to 1994, Dr. O worked at Analog Devices Inc. developing sub-micron CMOS processes for mixed signal applications, and high speed bipolar and BiCMOS processes. He was a professor at the University of Florida, Gainesville from 1994 to 2009.

  • He is currently the Director of Texas Analog Center of Excellence and Texas Instruments Distinguished University Chair Professor of Analog Circuits and Systems at the University of Texas at Dallas. His research group is developing circuits and components required to implement analog and digital systems operating at frequencies up to 40THz using silicon IC technologies.

  • Dr. O was the President of the IEEE Solid-State Circuits Society in 2020 and 2021.

  • He has authored and co-authored 290 journal and conference publications, as well as holding 15 patents.

  • Dr. O has received the 2014 Semiconductor Research Association University Researcher Award.

  • Prof. O is also an IEEE Fellow.


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