W7: MOS-AK workshop
16:00 - 18:00
MOS-AK Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/Spice modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme - frontiers of the compact modeling for nm-scale MEMS/NEMS designs, CMOS/SOI and HEMT IC simulation. The specific workshop goal will be to classify the most important directions for the future development of the electron device models, not limiting the discussion to compact models, but including physical, analytical and numerical models, to clearly identify areas that need further research and possible contact points between the different modeling domains. This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe, GaN, InP) who are interested in device modeling; ICs designers (RF/Analog/Mixed-Signal/SoC/Bio/Med) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind the IC simulation in modern device models, in particular using free open source PDKs.
Wladek Grabinski, MOS-AK (EU)
Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, Poland, in 1991. From 1991 to 1998 he was a Research Assistant at the Integrated Systems Lab, ETHZ, Switzerland, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPFL, and was engaged in the compact MOSFET model developments supporting numerical device simulation and parameter extraction. Later, he was a technical staff engineer at Motorola, and subsequently at FSL, GMC (CH). He is now a consultant responsible for SPICE modeling, characterization and parameter extraction of MOST devices for the analog/RF IC applications using FOSS CAD/EDA tool. He is an editor of the reference modeling book Transistor Level Modeling for Analog/RF IC Design, and also authored or coauthored more than 70 papers. Wladek has established ESSDERC Track3: "Compact Modeling and Process/Device Simulation" as well as has served as a member of organization committee and TPC of ESSDERC/ESSDERC, SBMicro, LADEC, SISPAD, MIXDES Conferences. He is an IEEE EDS R8 Vice Chair also supports the EPFL IEEE Student Branch. Wladek is involved in activities of the MOS-AK Association and serves as a coordinating manager since 1999.