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T3: Open-source neuromorphic circuit design
Overview, trends, and opportunities





10:00 - 12:30



Room 5A


As a bio-inspired alternative to conventional machine-learning accelerators, neuromorphic circuits outline promising energy savings for extreme-edge scenarios. While still being considered as an emerging approach, neuromorphic chip design is now being included in worldwide research roadmaps: the community is growing fast and is currently catalyzed by the development of open-source design tools and platforms. In this tutorial, we will survey the diversity of the open-source neuromorphic chip design landscape, from digital and mixed-signal small-scale proofs-of-concept to large-scale platforms. We will also provide a hands-on overview of the associated design challenges and guidelines, from which we will extract upcoming trends and promising use cases.


Charlotte Frenkel (Delft University of Technology, NL)

Charlotte Frenkel is an Assistant Professor at Delft University of Technology, The Netherlands. She received her Ph.D. from UC Louvain, Belgium, in 2020 and was a post-doctoral researcher at UZH and ETH Zürich, Switzerland. Her research aims at bridging the bottom-up (neuroscience-driven) and top-down (engineering-driven) neuromorphic design approaches, with a focus on digital spiking neural network processor design, embedded machine learning, and brain-inspired on-device learning. She received a best paper award at ISCAS 2020, and her Ph.D. thesis was awarded the FNRS / Nokia Bell Scientific Award 2021 and the FNRS / IBM Innovation Award 2021. She is the chair of the tinyML initiative on neuromorphic engineering, is a TPC member of ESSCIRC and DATE, and serves as an associate editor for the IEEE Trans. on Biomedical Circuits and Systems.



10:00 - 10:45

Digital neuromorphic circuit design for smart sensors

Charlotte Frenkel (Delft University of Technology, NL)

10:45 - 11:30

In-memory computing with spike-based neuromorphic systems

Jason Eshraghian (UC Santa Cruz, CA)

11:30 - 12:15

Large-scale neuromorphic systems with asynchronous logic

Rajit Manohar (Yale University, US)

12:15 - 12:30




Dr Jason Eshraghian is an assistant professor of Electrical and Computer Engineering at UC Santa Cruz. He is the developer of snnTorch, a widely adopted Python library used to train and model brain-inspired spiking neural networks. He was awarded the IEEE TCAS-I Darlington'23, IEEE TVLSI'19, and IEEE AICAS'19 best paper awards, and the best live demonstration award at IEEE ICECS'20. He was the recipient of the Fulbright Future Fellowship (Australian-America Fulbright Commission), the Forrest Research Fellowship (Forrest Research Foundation), and the Endeavour Fellowship (Australian Government). He leads the UCSC Neuromorphic Computing Group supported by Intel Labs and the NSF, focusing on advancing neuromorphic computing research. Dr Eshraghian is the Secretary of the IEEE Neural Systems and Applications Committee, and an Associate Editor with APL Machine Learning.

Rajit Manohar received the B.S., M.S., and Ph.D. degrees from the California Institute of Technology, Pasadena, CA, USA, in 1994, 1995, and 1998. From 1998 to 2016, he was a Stephen H. Weiss Presidential Fellow on the Faculty of Cornell University, Ithaca, NY, USA. Since 2017, he has been with the Yale Faculty, Yale University, New Haven, CT, USA, where his group conducts research on the design, analysis, and implementation of self-timed systems. He is currently the John C. Malone Professor of electrical engineering and a Professor of computer science at Yale University. He founded the Computer Systems Lab at both Cornell University and Yale University. His work includes the design and implementation of a number of self-timed VLSI chips, including the first high-performance asynchronous microprocessor, the first microprocessor for sensor networks, the first asynchronous dataflow field-programmable gate array (FPGA), the first radiation hardened SRAM-based FPGA, and the first deterministic large-scale neuromorphic architecture. Dr. Manohar was a recipient of the NSF CAREER award, ten best paper awards, and nine teaching awards, and was named MIT Technology Review's Top 35 Young Innovators Under 35 for his contributions to the low-power microprocessor design. 

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