Event

Tutorial

 

​When

Half day, 10:00

 

Where

Room 5

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Abstract

The demand for low-power SoCs in mobile consumer electronics is a main driver for CMOS scaling. For digital designs, the adoption of advanced CMOS process technologies offers clear power, performance, area, and cost (PPAC) benefits. However, porting analog/mixed-signal circuits to the latest process node only provides marginal PPAC benefits, and it comes at the expense of increased complexity and development time. Feature scaling translates to larger wire RC product, exacerbated layout-dependent effects, and reliability challenges. The analog/mixed-signal design space has gradually shifted from device-centric to interconnect-centric. In this workshop we will present the latest methodologies for modeling, design, simulation and debug of analog/mixed circuits. These methodologies lead to improved process portability, design and verification.

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Organiser

Pietro Caragiulo (Meta, IT)

Pietro Caragiulo pursued his Ph.D. degree in Electrical Engineering at Stanford University and Master and Bachelor degree at Politecnico di Bari. From 2010 to 2018, he was with the SLAC National Accelerator Laboratory, where he was involved in the development of high-frame-rate cameras and time-of-flight sensors. Dr. Caragiulo is the recipient of several awards, including the Stanford Graduate Fellowships (SGF) in Science and Engineering in 2018 and the ADI Outstanding Student Designer Award in 2020. He is currently a Silicon Research Scientist at Meta.