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W6: Source-gated transistors
The building block of next-generation thin-film edge processing systems





Half day, 13:30



Room 1.05


Source-gated transistors (SGTs) have a relatively long history of development but only recently have mainstream technologies allowed for their effective implementation at scale. This tutorial is addressed to those interested in efficient analog and mixed signal design with advanced thin-film transistors. It provides a development progression with a forward look toward SGT application to future edge processing of sensor data, signal conditioning, and current-mode driving. Crucially, the concept can be applied in practically any material system. As such, the tutorial will present the fundamentals of contact effect engineering and modelling, design rules for successful SGT implementation, specifics of performance optimisation in organic and oxide semiconductors, and structural evolutions for additional functionality.


Radu Sporea (University of Surrey, GB)

Dr Radu Sporea SMIEE MIET is Senior Lecturer in Power Electronics and Semiconductor Devices at the Advanced Technology Institute (ATI), University of Surrey and holds an EPSRC Early Career Fellowship (2021-2026).

Prior to this appointment he was Royal Academy of Engineering Academic Research Fellow (2011-2016), EPSRC PhD+ Fellow (2010-2011) and PhD researcher (2006 – 2010) in the same centre. Before joining Surrey, Radu has studied Computer Systems Engineering at “Politehnica” University, Bucharest, Romania, and has worked as a Design Engineer for Catalyst Semiconductor Romania, now part of ON Semiconductor, on ultra-low-power CMOS analog circuits. Radu’s was named an EPSRC Rising Star in 2014 and was the recipient of the I K Brunel Award for Engineering in 2015. He was presented the Vice Chancellor’s award for Early Career Teaching in 2017 and won the Tony Jeans Inspirational Teaching distinction in 2018. In 2021, he was a finalist of the Innovator of the Year prize at Surrey. Radu chaired the 17th International Thin Film Transistor Conference (ITC2022) held as a hybrid event on the University of Surrey campus.

Current research in Radu’s team focuses on three main topics:

1. Advanced large-area semiconductor device design, including transistors with increased tolerance to fabrication variability, improved energy efficiency and high gain.

2. Large area sensors and sensor arrays for smart environments, focusing on multi-modal low-cost integration in commercial manufacturing platforms and mass-market products.

3. Paper-based electronics and physical-digital interaction.


13:30 - 14:00

Contact Effects in Thin-Film Transistors: The Quest for Efficiency

Hagen Klauk (MPI, DE)

14:00 - 14:30

Compact modelling of thin-film transistors with non-negligible contact effects

Benjamin Iñiguez Nicolau (University Rovira i Virgili, ES)

14:30 - 15:00

Source-gated transistors: deliberately introducing and controlling contact effects

Radu Sporea (University of Surrey,  GB)

15:00 - 15:30

Organic thin-film source-gated transistors – fabrication and modelling

Antonio Valletta (IMM - CNR, IT)

15:30 - 16:00

Coffee Break

16:00 - 16:30

High-gain printed organic source-gated transistors and amplifiers

Hiroyuki Matsui (Yamagata University, JP)

16:30 - 17:00

High-gain and transparent oxide semiconductor transistors

Jiawei Zhang (Shandong University, CN)

17:00 - 17:30

The Multimodal Transistor for versatile analog computation

Radu Sporea (University of Surrey, GB)


Benjamin Iñiguez obtained the Ph D in Physics in 1992 and 1996, respectively, from the Universitat de les Illes Balears (UIB). From February 1997 to September 1998 he was working as a Postdoctoral Researcher at the Rensselaer Polytecnhnic Institute in Troy (NY, USA). From September 1998 to January 2001 he was working as a Postdoctoral Scientist in the Université catholiquede Louvain (Louvain-la-Neuve, Belgium), supported by two Marie Curie Fellowships from the European Commission. In February 2001 he joined the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA)of the  Universitat Rovira i Virgili (URV), in Tarragona, Catalonia, Spain) as Titular Professor. In February  2010 he became Full  Professor at URV. He obtained the Distinction from the Generalitat for the Promotion of University Research in 2004 and the ICREA Academia Award (the highest award for university professors in Catalonia, from ICREA Institute) in 2009 and 2014. He led two research projects funded by the European Union (EU) and has participated as URV team leader in four more EU-funded projects.   He has supervised or co-supervised 13 Ph D students. He has been the Chair Person of five international conferences and workshops devoted to advanced semiconductor devices, as well as four international training courses on device modeling. 

He is EDS Distinguished Lecturer since 2004, Editor of IEEE T-ED since August 2016, Chair of the EDS Compact Modeling Technical Council since January 2017, EDS BoG Member at Large since January 2018, and SRC Region 8 Vice-Chair since January 2020. In 2019 he was elected IEEE Fellow. 

His main  research interests are the characterization, parameter extraction and compact modelling of emerging semiconductor devices, in particular nanoscale Multi-Gate MOSFETs GaN HEMTs, and organic  and oxide Thin-Film Transistors. He has published more than 180 research papers in international journals and more than 170 abstracts in proceedings of conferences.

Antonio Valletta obtained his M.Sc. degree in Physics in 1997 from the University of Rome ‘La Sapienza’ and his Ph.D degree in 2003 from the University ‘RomaTRE’. He joined the Institute for Microelectronics and Microsystems of the Italian National Research Council (IMM-CNR) in 1999 and he is a member of the institute permanent staff from 2005. His research activity is focused on the characterization, simulation and physical modelling of semiconductor devices such as thin-film transistors (TFT and organic TFT), amorphous silicon photovoltaics devices, power transistors (SiC) and GaN based high electron mobility transistors (HEMT). He is also involved in the design and implementation of electrical compact models suitable for SPICE-like circuit simulation environments. He has co-authored over 100 scientific publications and holds an H-index of 26 (April 2023, source: Google Scholar).

Hiroyuki Matsui received his Ph.D. from Department of Advanced Materials Science, The University of Tokyo in 2011. After being appointed as Researcher at National Institute of Advanced Industrial Science and Technology (AIST) (2011-2013), Assistant Professor at The University of Tokyo (2013-2016), and Associate Professor at Yamagata University (2016-2023), he is currently Professor (2023-present) at Research Center for Organic Electronics (ROEL), Yamagata University, Japan. His research includes applied physics, circuit applications, and materials informatics of flexible and printed organic transistors and related devices.

Jiawei Zhang received his PhD degree in electronics from the University of Manchester in 2016. After 3 years of postdoc at National Graphene Institute in Manchester, he became a Professor at the School of Microelectronics, Shandong University in 2019. His research topic focuses on oxide-based thin-film transistors and THz electronics based on 2D materials.

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